Eduard Alarcón is a professor and educator, research scientist and student mentor at UPC BarcelonaTech, his alma mater, where he graduated MSc -national award-, and PhD in 1999. He is faculty of Telecommunication Engineering at UPC, where he was Associate Dean of International Affairs and is CFIS adjunct. Invited professor at KTH and CU Boulder. His cooperative research has resulted in 500 co-authored scientific publications, 7 books, 8 book chapters and 12 patents, in the scientific fields of on-chip energy and RF management, nanosatellites and satellite architectures for Earth Observation, nanotechnology-enabled graphene wireless communications for distributed computing, molecular communications, and AI-defined networks, areas in which he has been participating in EU, DARPA, NSF, NASA and ESA projects and awards with companies as Intel, Samsung and Google. Service includes EiC of IEEE JETCAS, General Chair of IEEE ISCAS 2020, and Vice President IEEE CAS.

Research interests

The overarching research vision can be synthesized as "Designing Complexity in Systems Interplaying Communications and Computing”. The pursuit is to crystallize a design methodology for systems with extreme complexity, including communication and computing functions with limited energy resources, of large scale, distributed architectures, heterogeneous components and strict system-wide performance attributes, through emergent technologies of communications, computing and processing. The need of design methodologies for systems of increasing complexity requires implementation-aware resource-constrained vertical crosslayer model-based designs. The aim is to instantiate this methodology of complex system design with resilient, evolvable and robust attributes to both future spacecraft architectures, and to future domain-specific computing platforms with built-in advanced wireless communications, by interplaying AI co-processor architectures and cognitive model-prediction schemes.

 

 

Keywords

Nanosatellite design. Nanocommunications: biomolecular and nanotechnogy-enabled. Wireless on-chip. Artificial Intelligence co-processors chips. Energy-constrained design.