Eduard Alarcón is a professor, research scientist and student mentor at UPC BarcelonaTech, his alma mater, where he graduated MSc -national award-, and PhD in 1999. He is faculty of Telecommunication Engineering at UPC, where he was Associate Dean of International Affairs and is CFIS adjunct. Invited professor at KTH and CU Boulder. His cooperative research has resulted in 500 co-authored scientific publications, 35 international invited lectures, 7 books and 12 patents in the scientific fields of on-chip energy management, nanosatellites and satellite architectures for EO, nanotechnology-enabled graphene wireless communications, and AI and Quantum processor architectures, areas in which he has participated in EU FET Open (3), H2020 Space, DARPA, NSF, NASA and ESA projects and awards with companies as Intel, Samsung and Google. Service includes EiC of IEEE JETCAS, General Chair of IEEE ISCAS 2020, Vice President IEEE CAS, and Vice President of Quantum Computing ThinkTank

Research interests

The overarching research vision can be synthesized as "Designing Complexity in Systems Interplaying Communications and ComputingâEUR. The pursuit is to crystallize a design methodology for systems with extreme complexity, including communication and computing functions with limited energy resources, of large scale, distributed architectures, heterogeneous components and strict system-wide performance attributes, through emergent technologies of communications, computing and processing. The need of structured design methodologies for systems of increasing complexity requires vertical crosslayer model-based approaches including AI surrogates. The aim is to instantiate this methodology of complex system design with resilient, evolvable and robust attributes to both future spacecraft architectures, and to future domain-specific computing platforms with built-in advanced wireless communications, encompassing Graph Neural Networks co-processors and Quantum Computing architectures.

Keywords

Wireless on-chip. Artificial Intelligence co-processors chips: Graph Neural Networks and In-memory computing. Quantum computing architectures. Nanosatellite constellation design. Energy-constrained design.